1. Field of the Invention
The present invention generally relates to pulse width modulation control in an inverter employed for speed control of a three phase AC motor, and more particularly to a system which controls the supply of the pulse width modulation signals so that three phase output voltage resultant vectors form a circular locus.
2. Description of the Prior Art
Several systems for supplying pulse width modulation signals have been known in prior art types of pulse width modulated voltage-source inverters employed for speed control of a three phase AC motor. One of such systems is disclosed in an article entitled "Improved PWM Method For Induction Motor Drive Inverters" published in the conference record of International Power Electronics Conference held in Tokyo on Mar. 27-31, 1983. In the prior art systems, in order that torque ripples may be lessened, the supply of the pulse width modulation signals is controlled so that a locus of three phase output voltage resultant vectors becomes a circle. FIG. 6 illustrates a three phase bridged inverter comprising six switching elements S.sub.1 -S.sub.6. As shown in FIG. 7, line voltage resultant vectors directed between respective phases U, V and W are of eight kinds, which number corresponds to the number of combination in on-off states of the switching elements S.sub.1 -S.sub.6, that is, the number of switching patterns. In each phase, each line voltage vector is split into two voltage vectors Va and Vb in accordance with the phase .theta., as shown in FIG. 8. Where the pulse width modulation signals are supplied so that the switching elements S.sub.1 -S.sub.6 are turned on and off in accordance with the switching patterns in which each line voltage resultant vector is split into two vectors Va and Vb, the locus of the three phase output voltage resultant vectors becomes a circle.
FIG. 9 shows a prior art control circuit emboding the above-described method of controlling the supply of pulse width modulation signals. A counter 1 counts clock pulses f.omega. which are proportional to an established frequency. The counter 1 in operation is latched by a latch circuit 2 and the content of the clock pulse f.omega. at the time when the counter 1 is latched represents the phase .theta. and is addressed as a higher address in a read only memory (hereinafter referred to as ROM) 3. A counter 4 counts reference clock pulses and the value gained by the counting operation of the counter 4 is addressed as a higher address in a ROM 5. A voltage command is addressed as a higher address in the ROM 5. A trapezoidal wave Ed provided by the ROM 5 is addressed as a lower address in the ROM 3. Data of the switching patterns in which the voltage resultant vectors corresponding to the output data of the ROM 5 and the phase .theta. are moved in the range of the electrical angle of 360.degree. are written in the ROM 3. The ROM 3 outputs data of the switching patterns in which the voltage vectors Va and Vb shown in FIG. 8 are supplied in accordance with the output data Ed of the ROM 5 and the phase .theta..
According to the above-described control circuit, however, when eight bits (corresponding to electrical angle resolution of approximately 1.4.degree.) are required for the phase .theta. stored in the ROM 3 and the output data Ed of the ROM 5, the ROM 3 needs to have a capacity of 64K bytes. The capacity of the ROM 3 is further increased as the resolution of the phase .theta. is enhanced. The ROM 5 also requires a capacity of 64K bytes where eight bits are required for the voltage command data and the counter 4 respectively. Consequently, the control circuit becomes complicated and expensive.